UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 526

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.5.13 Arbitration
to 1), communication among the master devices is performed as the number of clocks are adjusted until the data
differs. This kind of operation is called arbitration.
is set (1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high
impedance, which releases the bus.
stop condition is detected, etc.) and the ALD0 = 1 setting that has been made by software.
control.
524
Transfer lines
When several master devices simultaneously generate a start condition (when STT0 is set to 1 before STD0 is set
When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in IIC status register 0 (IICS0)
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a
For details of interrupt request timing, see 13.5.9
Remark
Master 1
Master 2
SDA0
SDA0
SDA0
SCL0
SCL0
SCL0
STD0: Bit 1 of IIC status register 0 (IICS0)
STT0: Bit 1 of IIC control register 0 (IICC0)
Figure 13-20. Arbitration Timing Example
CHAPTER 13 SERIAL INTERFACE IIC0
User’s Manual U17893EJ8V0UD
Interrupt request (INTIIC0) generation timing and wait
Master 1 loses arbitration
Hi-Z
Hi-Z