UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 758

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
(2) Serial interface: Serial array unit (3/18)
Notes 1.
Caution Select the normal input buffer for SIj and SCKj and the normal output mode for SOj by using the
Remarks 1.
756
SCKp cycle time
SCKp high-/low-level width
SIp setup time
(to SCKp↑)
SIp hold time
(from SCKp↑)
Delay time from SCKp↓ to
SOp output
(T
(c) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
A
2.
3.
4.
= −40 to +85°C, 1.8 V ≤ V
Parameter
PIMg and POMg registers.
2.
Note 1
Note 3
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SOp output line.
Note 2
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 2))
p: CSI number (p = 00, 01, 10, 20), g: PIM and POM number (g = 0, 4, 14),
j: CSI number for which communication at different potential can be selected (j = 01, 10, 20)
f
MCK
: Serial array unit operation clock frequency
CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
t
t
t
t
t
t
KCY2
KH2
KL2
SIK2
KSI2
KSO2
Symbol
,
DD
= EV
4.0 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
C = 30 pF
DD
≤ 5.5 V, V
User’s Manual U17893EJ8V0UD
DD
DD
DD
Note 4
≤ 5.5 V
< 4.0 V
< 2.7 V
Conditions
SS
4.0 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
= EV
16 MHz < f
f
16 MHz < f
f
MCK
MCK
SS
DD
DD
DD
≤ 16 MHz
≤ 16 MHz
= AV
≤ 5.5 V
< 4.0 V
< 2.7 V
MCK
MCK
SS
= 0 V)
1/f
f
MCK
6/f
8/f
6/f
8/f
6/f
MIN.
KCY2
80
MCK
MCK
MCK
MCK
MCK
+ 50
/2
TYP.
2/f
2/f
2/f
Standard Products
MCK
MAX.
MCK
MCK
+ 125
+ 45
+ 57
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns