UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 649

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) When LVI is OFF upon power application (option byte: LVIOFF = 1)
(when X1 oscillation
oscillation clock (f
Internal reset signal
Internal high-speed
V
system clock (f
POC
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 21
Remark V
= 1.59 V (TYP.)
High-speed
is selected)
Supply voltage
1.8 V
CPU
2.
3.
4.
5.
MX
IH
(V
Note 1
V
)
)
0 V
Operation
DD
LVI
LOW-VOLTAGE DETECTOR).
V
Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
)
The operation guaranteed range is 1.8 V ≤ V
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
If the rate at which the voltage rises to 1.8 V after power application is slower than 0.5 V/ms (MIN.),
input a low level to the RESET pin before the voltage reaches to 1.8 V, or set LVI to ON by default by
using an option byte (option byte: LVIOFF = 0).
The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
LVI
POC
stops
: LVI detection voltage
: POC detection voltage
specified by software.
Wait for oscillation
accuracy stabilization
Starting oscillation is
Wait for voltage
0.5 V/ms (MIN.)
stabilization
1.92 to 6.17 ms
Reset processing
Note 2
Set LVI to be
used for reset
Note 3
oscillation clock)
(internal high-speed
Normal operation
CHAPTER 20 POWER-ON-CLEAR CIRCUIT
and Low-Voltage Detector (1/2)
Note 5
User’s Manual U17893EJ8V0UD
Reset period
(oscillation
stop)
Reset processing (43 to 160 s)
Wait for oscillation
accuracy stabilization
used for interrupt
Set LVI to be
oscillation clock)
(internal high-speed
Normal operation
specified by software.
Starting oscillation is
DD
≤ 5.5 V. To make the state at lower than 1.8 V reset
Note 4
μ
Note 5
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
Wait for voltage
specified by software.
stabilization
Starting oscillation is
1.92 to 6.17 ms
Reset processing
used for reset
Set LVI to be
Note 3
oscillation clock)
(internal high-speed
Normal operation
Note 5
Operation stops
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