UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 666

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.4.2 When used as interrupt
(1) When detecting level of supply voltage (V
664
(a) When LVI default start function stopped is set (option byte: LVIOFF = 1)
• When starting operation
• When stopping operation
Figure 21-8 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <8> above.
Either of the following procedures must be executed.
•
•
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
Write 00H to LVIM.
Clear LVION to 0.
When using 8-bit memory manipulation instruction:
When using 1-bit memory manipulation instruction:
Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value).
Mask the LVI interrupt (LVIMK = 1).
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
Use software to wait for the following periods of time (Total 410
Confirm that “supply voltage (V
Clear the interrupt request flag of LVI (LVIIF) to 0.
Release the interrupt mask flag of LVI (LVIMK).
Execute the EI instruction (when vector interrupts are used).
(V
selection register (LVIS).
•
•
•
or “supply voltage (V
(LVIF) of LVIM.
DD
Operation stabilization time (10
Minimum pulse width (200
Detection delay time (200
)) (default value).
CHAPTER 21 LOW-VOLTAGE DETECTOR
DD
) < detection voltage (V
User’s Manual U17893EJ8V0UD
μ
μ
DD
s (MAX.))
DD
s (MIN.))
) ≥ detection voltage (V
)
μ
s (MAX.))
LVI
)” when detecting the rising edge of V
LVI
)” when detecting the falling edge of V
μ
s).
DD
, at bit 0
DD
,