UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 540

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

538
An example of the processing procedure of the slave with the INTIIC0 interrupt is explained below (processing
is performed assuming that no extension code is used). The INTIIC0 interrupt checks the status, and the
following operations are performed.
<1> Communication is stopped if the stop condition is issued.
<2> If the start condition is issued, the address is checked and communication is completed if the address
<3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I
Remark
Interrupt servicing completed
INTIIC0 generated
does not match.
processing returns from the interrupt (the ready flag is cleared).
remaining in the wait state.
Set ready flag
SPD0 = 1?
STD0 = 1?
<1> to <3> above correspond to <1> to <3> in Figure 13-27 Slave Operation Flowchart (2).
No
No
<3>
If the address matches, the communication mode is set, wait is cancelled, and
Figure 13-27. Slave Operation Flowchart (2)
Yes
Yes
CHAPTER 13 SERIAL INTERFACE IIC0
<1>
<2>
User’s Manual U17893EJ8V0UD
Set communication mode flag
Communication direction flag
Clear ready flag
COI0 = 1?
← TRC0
Yes
No
Clear communication direction
communication mode flag
flag, ready flag, and
2
C bus