UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 181

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6.2 Example of controlling internal high-speed oscillation clock
The following describes examples of clock setting procedures for the following cases.
(1) When restarting oscillation of the internal high-speed oscillation clock
(2) When using internal high-speed oscillation clock as CPU/peripheral hardware clock
(3) When stopping the internal high-speed oscillation clock
(1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clock
(2) Example of setting procedure when using internal high-speed oscillation clock as CPU/peripheral
(b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1
<1> Setting restart of oscillation of the internal high-speed oscillation clock (CSC register)
Note After a reset release, the internal high-speed oscillator automatically starts oscillating and the internal
hardware clock
<1> Restarting oscillation of the internal high-speed oscillation clock
Note This setting is required to resume the X1 clock oscillation when the high-speed system clock is in the
<1> Confirming the CPU clock status (CKC register)
<2> Setting of X1 clock oscillation stabilization time after restart of X1 clock oscillation
<3> Stopping the high-speed system clock (CSC register)
Caution Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop
When HIOSTOP is cleared to 0, the internal high-speed oscillation clock restarts oscillation.
(See 5.6.2 (1) Example of setting procedure when restarting internal high-speed oscillation clock).
high-speed oscillation clock is selected as the CPU/peripheral hardware clock.
CLS
Note The setting of <1> is not necessary when the internal high-speed oscillation clock is operating.
0
0
1
When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the
CPU clock to the subsystem clock or internal high-speed oscillation clock.
Prior to setting "1" to MSTOP, set the OSTS register to a value greater than the count value to be
confirmed with the OSTS register after X1 clock oscillation is restarted.
When MSTOP is set to 1, X1 oscillation is stopped (the input of the external clock is disabled).
This setting is not required in the external clock input mode.
X1 oscillation mode.
Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed
system clock.
peripheral hardware that is operating on the high-speed system clock.
MCS
0
1
×
Internal high-speed oscillation clock
High-speed system clock
Subsystem clock
CHAPTER 5 CLOCK GENERATOR
User’s Manual U17893EJ8V0UD
CPU Clock Status
Note
Note
Note
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