UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 892

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

890
2nd edition
3rd edition
Edition
• Modification of condition in upper part of table
• Modification of conditions and MAX. value of differential linearity error (DLE)
• Modification of condition in upper part of table
• Addition of D/A converter operating current (I
Deletion of description of Temperature Correction function of Internal High-Speed
Oscillation Clock and Temperature correction tables H, L from the following chapters.
• CHAPTER 3 CPU ARCHITECTURE
• CHAPTER 5 CLOCK GENERATOR
• CHAPTER 10 A/D CONVERTER
• CHAPTER 19 RESET FUNCTION
Change of status indication of
development”
1.1 Feature
• Addition of single-power supply flash memory security function
• Addition of flash shield window function to self-programming function
Changes of Figure 3-1 Memory Map (
Map (
Addition of 3.1.1(4) On-chip debug security ID setting area
Addition of Caution to 3.1.3 Internal data memory space
Addition of Caution to 3.2.4 Special function registers (SFRs)
Change of BCD adjust result register in Table 3-5 SFR List
Addition of Caution to 3.2.5 Extended special function registers (2nd SFRs: 2nd
Special Function Registers)
Change of Figure 5-1 Block Diagram of Clock Generator
Addition of Caution to Figure 5-7 Format of Peripheral Enable Register
Addition of Note 4 to 5.3 (7) Operation speed mode control register (OSMC)
Change of description of 5.3 (8) Internal high-speed oscillator trimming register
(HIOTRM)
Addition of time until CPU operation start in Figure 5-13 Clock Generator
Operation When Power Supply Voltage Is Turned On (When LVI Default Start
Function Stopped Is Set (Option Byte: LVIOFF = 1))
Change of Figure 5-14 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Enabled Is Set (Option Byte:
LVIOFF = 0))
Addition of Caution to 5.6.1 (3) <3>
Addition of Caution 2 to 6.3 (1) Peripheral enable register 0 (PER0)
Change of Figure 6-6 Format of Timer Mode Register 0n (TMR0n)
Addition of description to 6.3 (4) Timer status register 0n (TSR0n)
Addition of Table 6-3 OVF Bit Operation and Set/Clear Conditions in Each
Operation Mode
A/D Converter Characteristics
D/A Converter Characteristics
• Change of condition of Settling time (t
Addition of chapter.
• CHAPTER 28 ELECTRICAL SPECIFICATIONS (TARGET)
μ
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APPENDIX C REVISION HISTORY
μ
PD78F1152 and
User’s Manual U17893EJ8V0UD
Description
SET
μ
PD78F1152) through Figure 3-5 Memory
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DAC
μ
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PD78F1153 to “under
CHAPTER 28
ELECTRICAL
SPECIFICATIONS
(TARGET)
APPENDIX A
REVISION HISTORY
Throughout
CHAPTER 1 OUTLINE
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 6 TIMER
ARRAY UNIT
Chapter
(6/20)