UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 889

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2nd edition
Edition
Addition of an arrow from (C) to (B) in Figure 6-16 CPU Clock Status Transition
Diagram
Modification of Table 6-4 CPU Clock Transition and SFR Register Setting
Examples
Addition of description to Table 6-5 Changing CPU Clock
Modification of description in 6.6.7 Time required for switchover of CPU clock and
main system clock
Deletion of Caution in Table 6-8 Maximum Number of Clocks Required in Type 2
Change of bit name of TIS0n0 and TIS0n1 bits to CIS0n0 and CIS0n1 bits in
CHAPTER 7
Addition of description in 7.1.1 Functions of each channel when it operates
independently
Addition of description in 7.1.2 Functions of each channel when it operates with
another channel
Addition of description and table to 7.2 (1) Timer/counter register 0n (TCR0n)
Deletion of Caution in 7.2 (2) Timer data register 0n (TDR0n)
Addition of SFR name for the lower 8 bits of registers TSR0n, TE0, TS0, TT0, TPS0,
TO0, TOE0, TOL0, and TOM0 in 7.3 Registers Controlling Timer Array Unit
Addition of description in 7.3 (2) Timer clock select register 0 (TPS0)
Modification of description and change of setting in Figure 7-6 Format of Timer
Mode Register 0n (TMR0n)
Change of R/W attribute in Figure 7-9 Format of Timer Channel Start Register 0
(TS0)
Change of R/W attribute in Figure 7-10 Format of Timer Channel Stop Register 0
(TT0)
Modification of description in 7.3 (9) Timer output enable register 0 (TOE0)
Modification of description in 7.3 (10) Timer output register 0 (TO0)
Modification of description in 7.3 (11) Timer output level register 0 (TOL0)
Modification of Figure 7-16 Format of Input Switch Control Register (ISC)
Modification of Figure 7-20 Example of Basic Timing of Operation as Interval
Timer/Square Wave Output
Addition of Caution to 7.5.4 Operation as input pulse interval measurement
Modification of Figure 7-31 Block Diagram of Operation as Input Pulse Interval
Measurement
Change of bit name of TIS0n0 and TIS0n1 bits to CIS0n0 and CIS0n1 bits in
CHAPTER 7
Addition of Caution to 7.5.5 Operation as input signal high-/low-level width
measurement
Modification of description in 7.6.1 Operation as PWM function
Change of Remark in 7.6 Operation of Plural Channels of Timer Array Unit
Modification of description in Figure 7-43 Operation Procedure When PWM
Function Is Used
Modification of Figure 7-44 Block Diagram of Operation as One-Shot Pulse
Output Function
Modification of description in 7.6.3 Operation as multiple PWM output function
APPENDIX C REVISION HISTORY
User’s Manual U17893EJ8V0UD
Description
CHAPTER 6 CLOCK
GENERATOR
CHAPTER 7 TIMER
ARRAY UNIT
Chapter
(3/20)
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