r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 101

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r5f71374an80fpv

Manufacturer Part Number
r5f71374an80fpv
Description
32-bit Risc Microcomputer Superh?? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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5.1
5.1.1
Exception handling is started by four sources: resets, address errors, interrupts and instructions and
have the priority, as shown in table 5.1. When several exceptions are detected at once, they are
processed according to the priority.
Table 5.1
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and
Exception
Reset
Interrupt
Address error
Instruction
Address error
Interrupt
Address error
Interrupt
2. Instructions that change the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF,
Overview
Types of Exception Handling and Priority
BRAF.
TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR.
Types of Exceptions and Priority
Exception Source
Power-on reset
Manual reset
User break (break before instruction execution)
CPU address error (instruction fetch)
General illegal instructions (undefined code)
Illegal slot instruction (undefined code placed immediately after a
delayed branch instruction*
Trap instruction (TRAPA instruction)
CPU address error (data access)
User break (break after instruction execution or operand break)
DTC address error (data access)
NMI
IRQ
On-chip peripheral modules
Section 5 Exception Handling
1
or instruction that changes the PC value*
Rev. 1.00 Sep. 21, 2007 Page 75 of 1124
Section 5 Exception Handling
REJ09B0402-0100
2
)
Priority
High
Low

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