r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 568

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 14 Serial Communication Interface (SCI)
Rev. 1.00 Sep. 21, 2007 Page 542 of 1124
REJ09B0402-0100
Bit
5
4
3
Bit Name
TE
RE
MPIE
Initial
value
0
0
0
R/W
R/W
R/W
R/W
Receive Enable
Description
Transmit Enable
Enables or disables the SCI serial transmitter.
0: Transmitter disabled*
1: Transmitter enabled*
Notes: 1. The TDRE flag in SCSSR is fixed at 1.
Enables or disables the SCI serial receiver.
0: Receiver disabled*
1: Receiver enabled*
Notes: 1. Clearing RE to 0 does not affect the receive
Multiprocessor Interrupt Enable (only when MP = 1 in
SCSMR in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped and setting of the
RDRF, FER, and ORER status flags in SCSSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
to 0 and normal receiving operation is resumed. For
details, refer to section 14.4.4, Multiprocessor
Communication Function.
2. Serial transmission starts after writing
2. Serial reception starts when a start bit is
transmit data into SCTDR and clearing the
TDRE flag in SCSSR to 0 while the
transmitter is enabled. Select the transmit
format in the serial mode register (SCSMR)
before setting TE to 1.
flags (RDRF, FER, PER, and ORER). These
flags retain their previous values.
detected in asynchronous mode, or
synchronous clock input is detected in clock
synchronous mode. Select the receive
format in SCSMR before setting RE to 1.
2
1
2
1