r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 152

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 7 User Break Controller (UBC)
7.3.3
BBRA is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L
bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size
in the break conditions of channel A.
Initial value:
Rev. 1.00 Sep. 21, 2007 Page 126 of 1124
REJ09B0402-0100
Bit
31 to 0 BAMA31 to
Bit
15 to 11 
10 to 8 CPA[2:0]
R/W:
Bit:
Bit Name
BAMA 0
Bit Name
Break Bus Cycle Register A (BBRA)
15
R
0
-
14
R
0
-
13
R
0
-
Initial
Value
All 0
Initial
Value
All 0
000
12
R
0
-
11
R/W
R/W
R
R/W
R
R/W
0
-
R/W
10
0
CPA[2:0]
Description
Break Address Mask A
Specify bits masked in the channel A break address bits
specified by BARA (BAA31 to BAA0).
0: Break address bit BAAn of channel A is included in
1: Break address bit BAAn of channel A is masked and
Note: n = 31 to 0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Bus Master Select A for I Bus
Select the bus master when the I bus is selected as the
bus cycle of the channel A break condition. However,
when the L bus is selected as the bus cycle, the setting
of the CPA2 to CPA0 bits is disabled.
000: Condition comparison is not performed
xx1: The CPU cycle is included in the break condition
x1x: Setting prohibited
1xx: The DTC cycle is included in the break condition
R/W
9
0
the break condition
is not included in the break condition
R/W
8
0
R/W
7
0
CDA[1:0]
R/W
6
0
R/W
5
0
IDA[1:0]
R/W
4
0
R/W
3
0
RWA[1:0]
R/W
2
0
R/W
1
0
SZA[1:0]
R/W
0
0