r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 695

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

16.4.5
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 16.11 and 16.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS bit in ICMR and bits CKS3 to CKS0 in ICCR1.
2. When the slave address matches in the first frame following detection of the start condition,
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
4. The last byte data is read by reading ICDRR.
(Master output)
(Master output)
(Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait
until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address and R/W, it is not used.)
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
(Slave output)
(Slave output)
processing
ICDRS
ICDRR
RDRF
User
SCL
SDA
SDA
SCL
Slave Receive Operation
Figure 16.11 Slave Receive Mode Operation Timing (1)
[2] Read ICDRR (dummy read)
A
9
Bit 7
1
Data 1
Bit 6
2
Bit 5
3
Bit 4
4
Bit 3
5
Rev. 1.00 Sep. 21, 2007 Page 669 of 1124
Bit 2
6
Section 16 I
Bit 1
7
Bit 0
2
8
C Bus Interface 2 (I
[2] Read ICDRR
REJ09B0402-0100
A
9
Bit 7
Data 1
1
Data 2
2
C2)