r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 160

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 7 User Break Controller (UBC)
7.3.10
BBRB is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L
bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size
in the break conditions of channel B.
Initial value:
Rev. 1.00 Sep. 21, 2007 Page 134 of 1124
REJ09B0402-0100
Bit
15 to 11
10 to 8
7, 6
R/W:
Bit:
Break Bus Cycle Register B (BBRB)
15
R
0
Bit Name

CPB[2:0]
CDB[1:0]
-
14
R
0
-
13
R
0
-
Initial
Value
All 0
000
00
12
R
0
-
11
R
0
-
R/W
R
R/W
R/W
R/W
10
0
CPB[2:0]
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
L Bus Cycle/I Bus Cycle Select B
Select the L bus cycle or I bus cycle as the bus cycle
of the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
Bus Master Select B for I Bus
Select the bus master when the I bus is selected as
the bus cycle of the channel B break condition.
However, when the L bus is selected as the bus cycle,
the setting of the CPB2 to CPB0 bits is disabled.
000: Condition comparison is not performed
xx1: The CPU cycle is included in the break condition
x1x: Setting prohibited
1xx: The DTC cycle is included in the break condition
9
0
R/W
8
0
R/W
7
CDB[1:0]
0
R/W
6
0
R/W
5
0
IDB[1:0]
R/W
4
0
R/W
3
0
RWB[1:0]
R/W
2
0
R/W
1
0
SZB[1:0]
R/W
0
0