r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 661

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

(3)
Figure 15.15 shows an example of reception operation, and figure 15.16 shows a flowchart
example of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit in SSER to 1, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a transfer
clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF
bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
User operation
LSI operation
Data Reception
SSCK
RDRF
SSO
Dummy-read SSRDR
Bit 0
Figure 15.15 Example of Reception Operation
(Clock Synchronous Communication Mode)
1 frame
Bit 7
RXI interrupt
generated
Section 15 Synchronous Serial Communication Unit (SSU)
Bit 0
Read data from SSRDR
1 frame
Rev. 1.00 Sep. 21, 2007 Page 635 of 1124
RXI interrupt
generated
Bit 7
Bit 0
Read data from SSRDR
REJ09B0402-0100
Bit 7
RXI interrupt
generated