r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 210

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 8 Data Transfer Controller (DTC)
8.5.5
In block transfer mode, data are transferred in block units in response to a single activation
request. Either the transfer source or the transfer destination is designated as a block area by the
DTS bit in MRB.
The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the block data
transfer of one block ends, the block size counter (CRAL) and address register (SAR when DTS =
1 or DAR when DTS = 0) specified as the block area is restored to the initial state. The other
address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be
specified. When the specified number of transfers ends, an interrupt is requested to the CPU.
Table 8.8 lists the register function in block transfer mode. Figure 8.8 shows the memory map in
block transfer mode.
Table 8.8
Note:
Rev. 1.00 Sep. 21, 2007 Page 184 of 1124
REJ09B0402-0100
Register Function
SAR
DAR
CRAH
CRAL
CRB
*
Block Transfer Mode
Source address
Destination address
Block size storage
Block size counter
Block transfer counter
Transfer information writeback is skipped.
Register Function in Block Transfer Mode
Written Back Value
DTS = 0: Incremented/decremented/fixed*
DTS = 1: SAR initial value
DTS = 0: DAR initial value
DTS = 1: Incremented/decremented/fixed*
CRAH
CRAH
CRB − 1