r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 745

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

18.4
18.4.1
The CMT has channels and each of them to which a different vector address is allocated has
compare match interrupt. When both the interrupt request flag (CMF) and interrupt enable bit
(CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to
activate a CPU interrupt, the priority of channels can be changed by the interrupt controller
settings. For details, see section 6, Interrupt Controller (INTC).
The data transfer controller (DTC) can be activated by an interrupt request. In this case, the
priority between channels is fixed. See section 8, Data Transfer Controller (DTC), for details.
18.4.2
When CMCOR and CMCNT match, a compare match signal is generated and the CMF bit in
CMCSR is set to 1. The compare match signal is generated in the last cycle in which the values
match (when the CMCNT value is updated to H'0000). That is, after a match between CMCOR
and CMCNT, the compare match signal is not generated until the next CMCNT counter clock
input. Figure 18.4 shows the timing of CMF bit setting.
18.4.3
The CMF bit in CMCSR is cleared by reading 1 from this bit, then writing 0.
Interrupts
CMT Interrupt Sources and DTC Activation
Timing of Setting Compare Match Flag
Timing of Clearing Compare Match Flag
Peripheral operating
Compare match
Counter clock
clock (Pφ)
CMCOR
CMCNT
signal
Figure 18.4 Timing of CMF Setting
(N + 1)th
N
N
clock
Rev. 1.00 Sep. 21, 2007 Page 719 of 1124
Section 18 Compare Match Timer (CMT)
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