r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 72

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r5f71374an80fpv

Manufacturer Part Number
r5f71374an80fpv
Description
32-bit Risc Microcomputer Superh?? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Section 2 CPU
2.6
The CPU has the five processing states: reset, exception handling, bus release, program execution,
and power-down. Figure 2.4 shows the CPU state transition.
Rev. 1.00 Sep. 21, 2007 Page 46 of 1124
REJ09B0402-0100
RES = 0
Processing States
When internal power-on reset by WDT
or internal manual reset by WDT occurs.
From any state
when RES = 0
Bus request
generated
Bus release state
Power-on reset state
Figure 2.4 Transitions between Processing States
Bus request
generated
Bus request
cleared
Sleep mode
Bus request
cleared
RES = 1
Bus request
cleared
Bus request
generated
processing
From any state except
deep software standby mode
when RES = 1 and MRES = 0
Exception
source
occurs
SSBY bit = 0
execution state
for SLEEP
instruction
handling state
Exception
Program
RES = 0
Exception
processing
ends
SSBY bit = 1 and
STBYMD bit = 1
RES = 1,
MRES = 1
for SLEEP
instruction
Manual reset state
standby mode
Software
Reset state
NMI interrupt or IRQ
interrupt occurs
Deep software
standby mode
SSBY bit = 1 and
STBYMD bit = 0
for SLEEP
instruction
Power-down mode

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