r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 219

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Table 8.11 DTC Bus Release Timing
Notes: 1. The bus mastership is only released for the external space access request from the
Setting
Setting 1
Setting 2
Setting 3
Setting 4*
Setting 5
2
2. There are following restrictions in setting 4.
3. Don’t care.
DTLOCK CSSTP1
1
0
0
0
1
CPU after a vector read.
Bus Function Extending Register (BSCEHR)
•
•
•
•
0
0
1
1
1
Clock setting by the frequency control register (FRQCR) must be
Iφ:Bφ:Pφ:MIφ:MPφ = 8:4:4:4:4, 4:2:2:2:2, or 2:1:1:1:1.
Locate vector information in on-chip ROM or on-chip RAM.
Locate transfer information in on-chip RAM.
Transfer is allowed between on-chip RAM and on-chip peripheral module or
between external memory and on-chip peripheral module.
CSSTP2
*
0
*
*
*
Setting
3
3
3
3
CSSTP3
1
*
*
*
1
3
3
3
DTBST
0
0
0
1
0
After
vector
read
O
x
x
x
O
NOP cycle
generation*
O
O
x
x
x
(O: Bus is released; x: Bus is not released)
Rev. 1.00 Sep. 21, 2007 Page 193 of 1124
Section 8 Data Transfer Controller (DTC)
1
After
transfer
information
read
O
x
x
x
O
Bus Release Timing
After a
single
data
transfer
O
x
x
x
O
REJ09B0402-0100
After write-back of
transfer information
Normal
transfer
O
O
O
O
O
Continuous
transfer
O
O
O
x
O