r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 263

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

9.5.10
Table 9.10 shows the number of cycles required for access to the external memory by the CPU. As
the table shows, the number of cycles varies with the clock ratio, the access size, the external bus
width of the LSI, and the setting for wait insertion. For details on the wait-insertion setting, see
section 9.4, Register Descriptions.
Table 9.10 Number of External Access Cycles
Notes: n:
Synchronous logic and a layered bus structure have been adopted for this LSI circuit. Data on each
bus are input and output in synchronization with rising edges of the corresponding clock signal.
The L bus and I bus are synchronized with the Iφ and Bφ clocks, respectively. Figure 9.13 shows
an example of the timing of write access to a word of data over the external bus, with a bus-width
of 8 bits, when Iφ:Bφ = 2:1. Once the CPU has output the data to the L bus, data are transferred to
the I bus in synchronization with rising edges of Bφ. There are two Iφ clock cycles in a single Bφ
clock cycle when Iφ: Bφ = 2:1. Thus, when Iφ: Bφ = 2:1, data transfer from the L bus to the I bus
takes (1 + n) × Iφ (n = 0 to 1) (2 × Iφ is indicated in figure 9.13). The relation between the timing
of data output to the L bus and the rising edge of Bφ depends on the state of program execution.
Data output to the I bus are transferred to the external bus after one cycle of Bφ. External access to
each data takes at least two cycles, and this can be prolonged by the BSC register settings (m and
o in the formulae for number of access cycles). In the case shown in figure 9.13, since n = 1, m =
0, and o = 0, access takes 2 × Iφ + 3 × Bφ + 2 × Bφ.
External
Bus Width
8 bits
m, o:
Access to External Memory by CPU
Access
Size
Byte
Word
Longword
When Iφ:Bφ = 8:1, n = 0 to 7
When Iφ:Bφ = 4:1, n = 0 to 3
When Iφ:Bφ = 3:1, n = 0 to 2
When Iφ:Bφ = 2:1, n = 0 to 1
When Iφ:Bφ = 1:1, n = 0
m: Wait setting, o: Wait setting + idle setting
For details, see section 9.4, Register Descriptions.
Write/Read
Write
Read
Write
Read
Write
Read
Number of Access Cycles
(1 + n) × Iφ + (3 + m) × Bφ
(1 + n) × Iφ + (3 + m) × Bφ + 1 × Iφ
(1 + n) × Iφ + (3 + m) × Bφ + 1 × (2 + o) × Bφ
(1 + n) × Iφ + (3 + m) × Bφ + 1 × (2 + o) × Bφ+ 1 × Iφ
(1 + n) × Iφ + (3 + m) × Bφ + 3 × (2 + o) × Bφ
(1 + n) × Iφ + (3 + m) × Bφ + 3 × (2 + o) × Bφ+ 1 × Iφ
Rev. 1.00 Sep. 21, 2007 Page 237 of 1124
Section 9 Bus State Controller (BSC)
REJ09B0402-0100