r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 206

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 8 Data Transfer Controller (DTC)
8.5.1
By setting the RRS bit of DTCCR, the vector address read and transfer information read can be
skipped. The current DTC vector number is always compared with the vector number of previous
activation. If the vector numbers match when RRS = 1, a DTC data transfer is performed without
reading the vector address and transfer information. If the previous activation is a chain transfer,
the vector address read and transfer information read are always performed. Figure 8.5 shows the
transfer information read skip timing.
To modify the vector table and transfer information, temporarily clear the RRS bit to 0, modify the
vector table and transfer information, and then set the RRS bit to 1 again. When the RRS bit is
cleared to 0, the stored vector number is deleted, and the updated vector table and transfer
information are read at the next activation.
If the DTPR bit in the bus function extending register (BSCEHR) is set to 1, this function is
always disabled.
information read
Rev. 1.00 Sep. 21, 2007 Page 180 of 1124
REJ09B0402-0100
Internal address
Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.
DTC activation
Skip transfer
DTC request
Clock (Bφ)
request
Transfer Information Read Skip Function
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
(Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ =1: 1/2: 1/2;
Vector read
Figure 8.5 Transfer Information Read Skip Timing
Transfer Information is Written in 3 States)
Transfer information
read
transfer
Data
R
W
Transfer information
write
transfer
R
Data
W
Transfer information
write