r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 965

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r5f71374an80fpv

Manufacturer Part Number
r5f71374an80fpv
Description
32-bit Risc Microcomputer Superh?? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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The FLER bit is set to 1 in the following conditions:
• When the relevant bank area of flash memory is read during programming/erasing (including a
• When a SLEEP instruction (including software standby mode) is executed during
Error protection is cancelled (FLER bit is cleared) only by a power-on reset.
Note that the reset signal should only be released after providing a reset input over a period longer
than the normal 100 µs. Since high voltages are applied during programming/erasing of the flash
memory, some voltage may still remain even after the error protection state has been entered. For
this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset
period so that the charge is released.
The state-transition diagram in figure 22.16 shows transitions to and from the error protection
state.
vector read or an instruction fetch)
programming/erasing
Error occurred
Programming/erasing
Programming/erasing disabled
Error protection mode
Program mode
Figure 22.16 Transitions to and from Error Protection State
Read disabled
Erase mode
FLER = 0
enabled
Read enabled
FLER = 1
Software standby mode
software standby mode
RES = 0
Cancel
Programming/erasing disabled
Error protection mode
(Software standby)
Programming/erasing interface
register is in its initial state.
RES = 0
Programming/erasing disabled
Read disabled
(Hardware protection)
Rev. 1.00 Sep. 21, 2007 Page 939 of 1124
FLER = 1
Read enabled
FLER = 0
Reset
Programming/erasing interface
register is in its initial state.
Section 22 Flash Memory
REJ09B0402-0100

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