r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 706

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
16.6
In the I
address or the R/W bit, and the acknowledge bit may indicate the end of reception or reception of
the final frame, the continuous transfer of data by the DTC must be performed combined with the
CPU processing by the interrupt.
Table 16.5 shows some example of processing using the DTC. These examples assume that the
number of transfer data bytes is known in slave mode.
Table 16.5 Example of Processing Using DTC
Rev. 1.00 Sep. 21, 2007 Page 680 of 1124
REJ09B0402-0100
Item
Slave address +
R/W bit
transmission/
reception
Dummy data read 
Actual data
transmission/
reception
Last frame
processing
Setting of number
of DTC transfer
data frames
2
C bus format, since the slave device or the direction of transfer is selected by the slave
Operation Using the DTC
2
C Bus Interface 2 (I
Master Transmit
Mode
Transmission by
DTC (ICDR write)
Transmission by
DTC (ICDR write)
Not necessary
Transmission:
Actual data count
+ 1 (+ 1 equivalent
to slave address +
R/W bits)
2
C2)
Master Receive
Mode
Transmission by
CPU (ICDR write)
Processing by
CPU (ICDR read)
Reception by DTC
(ICDR read)
Reception by CPU
(ICDR read)
Reception: Actual
data count
Slave Transmit
Mode
Reception by CPU
(ICDR read)

Transmission by
DTC (ICDR write)
Not necessary
Transmission:
Actual data count
Slave Receive
Mode
Reception by CPU
(ICDR read)

Reception by DTC
(ICDR read)
Reception by CPU
(ICDR read)
Reception: Actual
data count