r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 20

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 17 A/D Converter (ADC) ..................................................................... 685
17.1 Features.............................................................................................................................. 685
17.2 Input/Output Pins............................................................................................................... 688
17.3 Register Descriptions......................................................................................................... 689
17.4 Operation ........................................................................................................................... 699
17.5 Interrupt Sources and DTC Transfer Requests .................................................................. 708
17.6 Definitions of A/D Conversion Accuracy.......................................................................... 709
17.7 Usage Notes ....................................................................................................................... 711
Section 18 Compare Match Timer (CMT) ........................................................ 713
18.1 Features.............................................................................................................................. 713
18.2 Register Descriptions......................................................................................................... 714
18.3 Operation ........................................................................................................................... 718
18.4 Interrupts............................................................................................................................ 719
Rev. 1.00 Sep. 21, 2007 Page xx of xxvi
17.3.1 A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1) ................................. 690
17.3.2 A/D Status Registers_0 and _1 (ADSR_0 and ADSR_1)..................................... 693
17.3.3 A/D Start Trigger Select Registers_0 and _1
17.3.4 A/D Analog Input Channel Select Registers_0 and _1
17.3.5 A/D Data Registers 0 to 15 (ADDR0 to ADDR15).............................................. 697
17.3.6 CPU Interface ....................................................................................................... 698
17.4.1 Single-Cycle Scan Mode ...................................................................................... 699
17.4.2 Continuous Scan Mode......................................................................................... 701
17.4.3 Input Sampling and A/D Conversion Time .......................................................... 703
17.4.4 A/D Converter Activation by MTU2 and MTU2S ............................................... 705
17.4.5 External Trigger Input Timing.............................................................................. 706
17.4.6 Example of ADDR Auto-Clear Function.............................................................. 706
17.7.1 Analog Input Voltage Range ................................................................................ 711
17.7.2 Relationship between AVcc, AVss and Vcc, Vss................................................. 711
17.7.3 Range of AV
17.7.4 Notes on Board Design ......................................................................................... 711
17.7.5 Notes on Noise Countermeasures ......................................................................... 712
17.7.6 Notes on Register Setting ..................................................................................... 712
18.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 715
18.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 715
18.2.3 Compare Match Counter (CMCNT)..................................................................... 717
18.2.4 Compare Match Constant Register (CMCOR) ..................................................... 717
18.3.1 Interval Count Operation ...................................................................................... 718
18.3.2 CMCNT Count Timing......................................................................................... 718
(ADSTRGR_0 and ADSTRGR_1)....................................................................... 694
(ADANSR_0 and ADANSR_1) ........................................................................... 696
refh
and AV
refl
Pin Settings ................................................................. 711