r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 710

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
16.8.4
1. Transfer rate setting
2. MST and TRS bits in ICCR1
3. Loss of arbitration
16.8.5
In master receive mode, read ICDRR before the rising edge of the 8th clock of SCL. If ICDRR
cannot be read before the rising edge of the 8th clock so that the next round of reception proceeds
with the RDRF bit in ICSR set to 1, the 8the clock is fixed low and the 9th clock is output.
If ICDRR cannot be read before the rising edge of the 8th clock of SCL, set the RCVD bit in
ICRR1 to 1 so that transfer proceeds in byte units.
16.8.6
The E200F emulator does not support I
I
Rev. 1.00 Sep. 21, 2007 Page 684 of 1124
REJ09B0402-0100
2
C2 operation.
In multi-master operation, specify a transfer rate of at least 1/1.8 of the fastest transfer rate
among the other masters. For example, when the fastest of the other masters is at 400 kbps, the
IIC transfer rate of this LSI must be specified as 223 kbps (= 400/1.8) or a higher rate.
In multi-master operation, use the MOV instruction to set the MST and TRS bits in ICCR1.
When arbitration is lost, check whether the MST and TRS bits in ICCR1 are 0. If the MST and
TRS bits in ICCR1 have been set to a value other than 0, clear the bits to 0.
Settings for Multi-Master Operation
Reading ICDRR in Master Receive Mode
Supported Emulator
2
C Bus Interface 2 (I
2
C2)
2
C2 operation. Use the E10A emulator when debugging the