r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 654

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 15 Synchronous Serial Communication Unit (SSU)
(4)
Figure 15.9 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1.
Rev. 1.00 Sep. 21, 2007 Page 628 of 1124
REJ09B0402-0100
Note: Hatching boxes represent SSU internal operations.
[1]
[2]
[4]
[5]
[6]
No
Data Transmission/Reception
Read received data in SSRDR
Read receive data in SSRDR
Consecutive data reception?
RDRF automatically cleared
Overrun error processing
Clear ORER in SSSR
Dummy-read SSRDR
Figure 15.8 Flowchart Example of Data Reception (SSU Mode)
End reception
End reception
Initial setting
Read SSSR
RDRF = 1?
ORER = 1?
RE = 0
Start
Yes
Yes
No
Yes
No
[3]
[1]
[2]
[3], [6] Receive error processing:
[4]
[5]
Initial setting:
Specify the receive data format.
Start reception:
When SSRDR is dummy-read with RE = 1, reception is
started.
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
To continue single reception:
When continuing single reception, wait for time of t
while the RDRF flag is set to 1 and then read receive data
in SSRDR.
The next single reception starts after reading receive data
in SSRDR.
To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
SUcyc