r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 245

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Bit
9
8
7 to 0
Bit Name
CSSTP3
DTPR

Initial
Value
0
0
All 0
R/W
R/W
R/W
R
Description
Select Priority for External Memory Access by CPU
Specifies whether or not access to the external space by
the CPU takes priority over DTC transfer.
0: DTC transfer has priority.
1: External space access from the CPU has priority.
Note: When this bit is 0, and access to internal I/O from
Application of Priority in DTC Activation
When multiple DTC activation requests are generated
before the DTC is activated, specify whether transfer
starts from the first request to have been generated or is
in accord with the priority order for DTC activation
requests.
However, when multiple DTC activation requests have
been issued while the DTC is active, the next transfer to
be triggered will be that with the highest DTC activation
priority.
0: Start transfer in response to the first request to have
1: Start transfer in accord with DTC activation request
Notes: When this bit is set to 1, the following restrictions
Reserved
These bits are always read as 0. The write value should
always be 0.
been generated.
priority.
the CPU is immediately followed by access to
external space from the CPU, a NOP 1Bφ in
duration is inserted between the two access cycles.
apply.
1. The vector information must be in on-chip ROM
2. The transfer information must be in on-chip
3. Skipping of transfer information reading is
or on-chip RAM.
RAM.
always disabled.
Rev. 1.00 Sep. 21, 2007 Page 219 of 1124
Section 9 Bus State Controller (BSC)
REJ09B0402-0100