r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 621

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

14.7.3
Break signals can be detected by reading the RXD pin directly when a framing error (FER) is
detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set
and the parity error flag (PER) may also be set. Note that, although transfer of receive data to
SCRDR is halted in the break state, the SCI receiver continues to operate.
14.7.4
The I/O condition and level of the TXD pin are determined by the SPB0IO and SPB0DT bits in
the serial port register (SCSPTR). This feature can be used to send a break signal.
Until TE bit is set to 1 (enabling transmission) after initializing, TXD pin does not work. During
the period, mark status is performed by SPB0DT bit. Therefore, the SPB0IO and SPB0DT bits
should be set to 1 (high level output).
To send a break signal during serial transmission, clear the SPB0DT bit to 0 (low level), then clear
the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized
regardless of the current transmission state, and 0 is output from the TXD pin.
14.7.5
The SCI operates on a base clock with a frequency of 16 times the transfer rate in asynchronous
mode. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples
on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The
timing is shown in figure 14.21.
Break Detection and Processing
Sending a Break Signal
Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)
Section 14 Serial Communication Interface (SCI)
Rev. 1.00 Sep. 21, 2007 Page 595 of 1124
REJ09B0402-0100