r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 142

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 6 Interrupt Controller (INTC)
Table 6.4
Notes: *
Rev. 1.00 Sep. 21, 2007 Page 116 of 1124
REJ09B0402-0100
Item
DTC active judgment
Interrupt priority decision
and comparison with mask
bits in SR
Wait for completion of
sequence currently being
executed by CPU
Time from start of interrupt
exception handling until
fetch of first instruction of
exception handling routine
starts
Interrupt
response
time
In the case that m1 = m2 = m3 = m4 = 1 × Icyc.
m1 to m4 are the number of cycles needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
Interrupt Response Time
Minimum*:
Maximum:
Total:
NMI

1 × Icyc + 2 ×
Pcyc
X (≥ 0)
8 × Icyc +
m1 + m2 + m3
9 × Icyc + 2 ×
Pcyc + m1 + m2
+ m3 + X
12 × Icyc +
2 × Pcyc
16 × Icyc +
2 × Pcyc + 2 ×
(m1 + m2 + m3)
+ m4
Number of Cycles
IRQ
2 × Bcyc
1 × Icyc + 1 ×
Pcyc
X (≥ 0)
8 × Icyc +
m1 + m2 + m3
9 × Icyc + 1 ×
Pcyc +2 × Bcyc +
m1 + m2 + m3 +
X
12 × Icyc +
1 × Pcyc +
2 × Bcyc
16 × Icyc +
1 × Pcyc +
2 × Bcyc + 2 ×
(m1 + m2 + m3)
+ m4
Peripheral
Modules
1 × Pcyc
1 × Icyc + 2 ×
Pcyc
X (≥ 0)
8 × Icyc +
m1 + m2 + m3
9 × Icyc + 3 ×
Pcyc + m1 + m2
+ m3 + X
12 × Icyc +
3 × Pcyc
16 × Icyc +
3 × Pcyc + 2 ×
(m1 + m2 + m3)
+ m4
Remarks
The longest sequence is
for interrupt or address-
error exception handling
(X = 7 × Icyc + m1 + m2
+ m3 + m4). If an
interrupt-masking
instruction follows,
however, the time may
be even longer.
Performs the saving PC
and SR, and vector
address fetch.
SR, PC, and vector table
are all in on-chip RAM.