r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 610

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 14 Serial Communication Interface (SCI)
Rev. 1.00 Sep. 21, 2007 Page 584 of 1124
REJ09B0402-0100
Note:
No
No
No
When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the
TE bit and RE bit to 0, then set both these bits to 1 simultaneously.
Clear TE and RE bits in SCSCR to 0
Start of transmission and reception
Write transmit data to SCTDR, and
Figure 14.14 Sample Flowchart for Transmitting/Receiving Serial Data
Write transmit data to SCTDR and
End of transmission and reception
clear TDRE flag in SCSSR to 0
clear TDRE flag in SCSSR to 0
Read ORER flag in SCSSR
Read TDRE flag in SCSSR
Read RDRF flag in SCSSR
All data received?
ORER = 1?
TDRE = 1?
RDRF = 1?
Yes
Yes
Yes
No
Error processing
Yes
[1]
[2]
[3]
[4]
SCI status check and transmit data write:
Read SCSSR and check that the TDRE flag is
set to 1, then write transmit data to SCTDR and
clear the TDRE flag to 0.
Transition of the TDRE flag from 0 to 1 can also
be identified by a TXI interrupt.
Receive error processing:
If a receive error occurs, read the ORER flag in
SCSSR, and after performing the appropriate
error processing, clear the ORER flag to 0.
Reception cannot be resumed if the ORER flag
is set to 1.
SCI status check and receive data read:
Read SCSSR and check that the RDRF flag is
set to 1, then read the receive data in SCRDR
and clear the RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be identified by
an RXI interrupt.
Serial transmission/reception continuation
procedure:
To continue serial transmission/reception,
before the MSB (bit 7) of the current frame is
received, finish reading the RDRF flag, reading
SCRDR, and clearing the RDRF flag to 0. Also,
before the MSB (bit 7) of the current frame is
transmitted, read 1 from the TDRE flag to
confirm that writing is possible. Then write data
to SCTDR and clear the TDRE flag to 0.
Checking and clearing of the TDRE flag is
automatic when the DTC is activated by a
transmit data empty interrupt (TXI) request and
data is written to SCTDR. Also, the RDRF flag
is cleared automatically when the DTC is
activated by a receive data full interrupt (RXI)
request and the SCRDR value is read.