r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 638

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 15 Synchronous Serial Communication Unit (SSU)
15.3.6
SSCR2 is a register that selects the assert timing of the SCS pin, data output timing of the SSO
pin, and set timing of the TEND bit.
Rev. 1.00 Sep. 21, 2007 Page 612 of 1124
REJ09B0402-0100
Bit
7 to 5
4
3
2
1, 0
Bit Name

TENDSTS 0
SCSATS
SSODTS

SS Control Register 2 (SSCR2)
Initial
Value
All 0
0
0
All 0
Initial value:
R/W:
Bit:
R/W
R
R/W
R/W
R/W
R
R
7
0
-
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Selects the timing of setting the TEND bit (valid in SSU
and master mode).
0: Sets the TEND bit when the last bit is being
1: Sets the TEND bit after the last bit is transmitted
Selects the assertion timing of the SCS pin (valid in
SSU and master mode).
0: Min. values of t
1: Min. values of t
Selects the data output timing of the SSO pin (valid in
SSU and master mode)
0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
Reserved
These bits are always read as 0. The write value should
always be 0.
R
5
0
-
transmitted
= 1, TE = 1, and RE = 0, the SSO pin outputs data
= 1, TE = 1, and RE = 0, the SSO pin outputs data
while the SCS pin is driven low
TENDSTS
R/W
4
0
SCSATS SSODTS
R/W
3
0
LEAD
LEAD
R/W
2
0
and t
and t
R
1
0
-
LAG
LAG
are 1/2 × t
are 3/2 × t
R
0
0
-
SUcyc
SUcyc