r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 188

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 8 Data Transfer Controller (DTC)
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x:
Rev. 1.00 Sep. 21, 2007 Page 162 of 1124
REJ09B0402-0100
Bit
5
4
3, 2
1, 0
Don't care
Bit Name
DISEL
DTS
DM[1:0]

Initial
Value
Undefined 
Undefined 
Undefined 
Undefined 
R/W
Description
DTC Interrupt Select
When this bit is set to 1, an interrupt request is generated
to the CPU every time a data transfer or a block transfer
ends. When this bit is set to 0, a CPU interrupt request is
only generated when the specified number of data
transfers end.
DTC Transfer Mode Select
Specifies either the source or destination as repeat or
block area during repeat or block transfer mode.
0: Specifies the destination as repeat or block area
1: Specifies the source as repeat or block area
Destination Address Mode 1 and 0
Specify a DAR operation after a data transfer.
0x: DAR is fixed
10: DAR is incremented after a transfer
11: SAR is decremented after a transfer
Reserved
The write value should always be 0.
(DAR writeback is skipped)
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)