r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 752

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 19 Controller Area Network (RCAN-ET)
Important: Although core of RCAN-ET is designed based on a 32-bit bus system, the whole
RCAN-ET including MPI for the CPU has 16-bit bus interface to CPU. In that case, LongWord
(32-bit) access must be implemented as 2 consecutive word (16-bit) accesses. In this manual,
LongWord access means the two consecutive accesses.
• Micro Processor Interface (MPI)
• Mailbox
• Mailbox Control
Rev. 1.00 Sep. 21, 2007 Page 726 of 1124
REJ09B0402-0100
The MPI allows communication between the Renesas CPU and RCAN-ET’s
registers/mailboxes to control the memory interface. It also contains the Wakeup Control logic
that detects the CAN bus activities and notifies the MPI and the other parts of RCAN-ET so
that the RCAN-ET can automatically exit the Sleep mode.
It contains registers such as MCR, IRR, GSR and IMR.
The Mailboxes consists of RAM configured as message buffers and registers. There are 16
Mailboxes, and each mailbox has the following information.
<RAM>
 CAN message control (identifier, rtr, ide,etc)
 CAN message data (for CAN Data frames)
 Local Acceptance Filter Mask for reception
<Registers>
 CAN message control (dlc)
 3-bit wide Mailbox Configuration, Disable Automatic Re-Transmission bit, Auto-
The Mailbox Control handles the following functions:
 For received messages, compare the IDs and generate appropriate RAM addresses/data to
 To transmit messages, RCAN-ET will run the internal arbitration to pick the correct
 Arbitrates Mailbox accesses between the CPU and the Mailbox Control.
 Contains registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, UMSR and
Transmission for Remote Request bit, New Message Control bit
store messages from the CAN Interface into the Mailbox and set/clear appropriate registers
accordingly.
priority message, and load the message from the Mailbox into the Tx-buffer of the CAN
Interface and set/clear appropriate registers accordingly.
MBIMR.