r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 281

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Bit
5
4
3 to 0
Bit Name
BFB
BFA
MD[3:0]
Initial
Value
0
0
0000
R/W
R/W
R/W
R/W
Description
Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare do not
take place in modes other than complementary PWM
mode, but compare match with TGRD occurs in
complementary PWM mode. Since the TGFD flag will
be set if a compare match occurs during Tb interval in
complementary PWM mode, the TGIED bit in timer
interrupt enable register 3/4 (TIER_3/4) should be
cleared to 0.
In channels 1 and 2, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB and TGRD operate normally
1: TGRB and TGRD used together for buffer operation
Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together for
buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare do not
take place in modes other than complementary PWM
mode, but compare match with TGRC occurs in
complementary PWM mode. Since the TGFC flag will
be set if a compare match occurs on channel 4 during
Tb interval in complementary PWM mode, the TGIEC
bit in timer interrupt enable register 4 (TIER_4) should
be cleared to 0.
In channels 1 and 2, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be modified.
0: TGRA and TGRC operate normally
1: TGRA and TGRC used together for buffer operation
Modes 0 to 3
These bits are used to set the timer operating mode.
See table 10.11 for details.
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 1.00 Sep. 21, 2007 Page 255 of 1124
REJ09B0402-0100