r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 260

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 9 Bus State Controller (BSC)
9.5.7
(1)
The bus state controller (BSC) can be initialized completely only at a power-on reset. At a power-
on reset, all signals are negated and output buffers are turned off regardless of the bus cycle state.
All control registers are initialized.
In standby, sleep, and manual reset, control registers of the bus state controller are not initialized.
At a manual reset, the current bus cycle being executed is completed and then the access wait state
is entered. However, a bus arbitration request by the BREQ signal cannot be accepted during
manual reset signal assertion.
(2)
There are three types of LSI internal buses: L bus, I bus, and peripheral bus. The CPU is
connected to the L bus. The DTC and bus state controller are connected to the I bus. Low-speed
peripheral modules are connected to the peripheral bus. On-chip memories are connected
bidirectionally to the L bus and I bus.
For an access of an external space or an on-chip peripheral module, the access is initiated via the I
bus. Thus, the DTC can be activated without bus arbitration with the CPU while the CPU is
accessing an on-chip memory.
Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an
access via the I bus before the previous external bus cycle is completed in a write cycle. If the on-
chip peripheral module is read or written after the external low-speed memory is written, the on-
chip peripheral module can be accessed before the completion of the external low-speed memory
write cycle.
In read cycles, the CPU is placed in the wait state until read operation has been completed. To
continue the process after the data write to the device has been completed, perform a dummy read
to the same address to check for completion of the write before the next process to be executed.
The write buffer of the BSC functions in the same way for an access by the DTC.
Since access cannot be performed correctly if any BSC register values are modified while the
write buffer is operating, do not modify BSC registers immediately after a write access. If the BSC
register need to be modified immediately after a write access, execute dummy read to confirm the
completion of the write access, then modify the BSC register.
Rev. 1.00 Sep. 21, 2007 Page 234 of 1124
REJ09B0402-0100
Reset
Access in View of LSI Internal Bus Master
Others