r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 176

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 7 User Break Controller (UBC)
(Example 1-3)
• Register specifications
(Example 1-4)
• Register specifications
Rev. 1.00 Sep. 21, 2007 Page 150 of 1124
REJ09B0402-0100
<Channel B>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
After an instruction with address H'00037226 is executed, a user break occurs before an
instruction with address H'0003722E is executed.
BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BDRA = H'00000000,
BDMRA = H'00000000, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054,
BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000000
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/write/word
<Channel B>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not
On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B,
no user break occurs since instruction fetch is performed for an even address.
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BDRA = H'00000000,
BDMRA = H'00000000, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056,
BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008
Specified conditions: Channel A/channel B sequential mode
<Channel A>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/write/word
H'0003722E, Address mask: H'00000000
H'00000000, Data mask: H'00000000
H'00027128, Address mask: H'00000000
H'00000000, Data mask: H'00000000
H'00031415, Address mask: H'00000000
H'00000000, Data mask: H'00000000
included in the condition)
H'00037226, Address mask: H'00000000
H'00000000, Data mask: H'00000000