r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 181

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

7. User breaks are disabled during UBC module standby mode. Do not read from or write to the
8. Do not set a post-execution break at a SLEEP instruction or a branch instruction for which a
9. The UBC cannot detect external space accesses by the CPU on the I bus correctly when the
UBC registers during UBC module standby mode; the values are not guaranteed.
SLEEP instruction is placed in the delay slot. In addition, do not set a data access break at a
SLEEP instruction or one or two instructions before a SLEEP instruction.
DTC is in operation. Select all bus masters when determining an external space access on the I
bus in the above condition. In this case, conditions for an identified bus master cannot be set.
However, if the bus master can be inferred from the data value, the bus master can be inferred
by including the data as a match condition.
Rev. 1.00 Sep. 21, 2007 Page 155 of 1124
Section 7 User Break Controller (UBC)
REJ09B0402-0100