r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 729

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

17.4.3
The A/D_0 has a built-in sample-and-hold circuit common to all the channels. Each of channels 0
to 2 of the A/D_0 has a dedicated built-in sample-and-hold circuit. Channels 0 to 2 can be
simultaneously sampled as one group. This group is referred to as Group A (GrA) (in table 17.5).
Even when only one channel is selected in the group by ADANSR, the sample-and-hold operation
is performed with the dedicated sample-and-hold circuit. When only the channels without a
dedicated sample-and-hold circuit are specified by ADANSR, the time that elapses is the same as
when a dedicated sample-and-hold circuit is used.
The above descriptions is the same with the A/D_1.
When an event that sets the ADST bit writing to this bit by the CPU, A/D converter activation
request from the MTU2, the MTU2S, and an external trigger signal occurs, the analog input is
sampled by the dedicated sample-and-hold circuit for each channel after the A/D conversion start
delay time (t
sampling of the analog input using the sample-and-hold circuit common to all the channels is
performed and then the A/D conversion is started. Figure 17.5 shows the A/D conversion timing in
this case. This A/D conversion time (t
(t
(t
channels (t
In continuous scan mode, the A/D conversion time (t
conversion time of the first cycle. The conversion time of the second and subsequent cycles is
expressed as (t
OFC
SPLSH
), the analog input sampling time with a dedicated sample-and-hold circuit for each channel
), and the analog input sampling time with the sample-and-hold circuit common to all the
Input Sampling and A/D Conversion Time
SPL
D
). The t
) has passed and the offset canceling processing (OFC) is performed. After this, the
CONV
− t
SPLSH
D
+ 6).
does not depend on the number of channels simultaneously sampled.
CONV
) includes the t
CONV
D
) given in table 17.6 applies to the
, the offset canceling processing time
Rev. 1.00 Sep. 21, 2007 Page 703 of 1124
Section 17 A/D Converter (ADC)
REJ09B0402-0100