r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 809

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

19.8
19.8.1
The clock supply to RCAN-ET can be stopped or started by using the standby control register 3
(STBCR3). With the initial value, the clock supply is stopped. Access to the RCAN-ET registers
should be made only after releasing RCAN-ET from module stop mode.
19.8.2
RCAN-ET can be reset by hardware reset or software reset.
• Hardware reset
• Software reset
Since the IRR0 bit in Interrupt Request Register (IRR) is set by the initialization upon reset, it
should be cleared while RCAN-ET is in configuration mode during the reset sequence.
The areas except for message control field 1 (CONTROL1) of mailboxes are not initialized by
reset because they are in RAM. After power-on reset, all mailboxes should be initialized while
RCAN-ET is in configuration mode during the reset sequence.
19.8.3
In CAN sleep mode, the clock supply to the major parts in the module is stopped. Therefore, do
not make access in CAN sleep mode except for access to the MCR, GSR, IRR, and IMR registers.
19.8.4
If the mailbox area is accessed while the CAN communication circuitry in RCAN-ET is storing a
received CAN bus frame in a mailbox, a 0 to five peripheral clock cycles of wait state is
generated.
RCAN-ET is reset to the initial state by power-on reset or on entering module stop mode or
software standby mode.
the MCR0 bit, and the CAN communication circuitry are initialized.
By setting the MCR0 bit in Master Control Register (MCR), RCAN-ET registers, excluding
Usage Notes
Module Stop Mode
Reset
CAN Sleep Mode
Register Access
Section 19 Controller Area Network (RCAN-ET)
Rev. 1.00 Sep. 21, 2007 Page 783 of 1124
REJ09B0402-0100