r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 767

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

If MCR2 is cleared, all messages for transmission are queued with respect to their priority (by
running internal arbitration). The highest priority message has the Arbitration Field (STDID + IDE
bit + EXTID (if IDE=1) + RTR bit) with the lowest digital value and is transmitted first. The
internal arbitration includes the RTR bit and the IDE bit (internal arbitration works in the same
way as the arbitration on the CAN Bus between two CAN nodes starting transmission at the same
time).
This bit can be modified only in Reset or Halt mode.
Bit 1—Halt Request (MCR1): Setting the MCR1 bit causes the CAN controller to complete its
current operation and then enter Halt mode (where it is cut off from the CAN bus). The RCAN-ET
remains in Halt Mode until the MCR1 is cleared. During the Halt mode, the CAN Interface does
not join the CAN bus activity and does not store messages or transmit messages. All the user
registers (including Mailbox contents and TEC/REC) remain unchanged with the exception of
IRR0 and GSR4 which are used to notify the halt status itself. If the CAN bus is in idle or
intermission state regardless of MCR6, RCAN-ET will enter Halt Mode within one Bit Time. If
MCR6 is set, a halt request during Bus Off will be also processed within one Bit Time. Otherwise
the full Bus Off recovery sequence will be performed beforehand. Entering the Halt Mode can be
notified by IRR0 and GSR4.
If both MCR14 and MCR6 are set, MCR1 is automatically set as soon as RCAN-ET enters
BusOff.
In the Halt mode, the RCAN-ET configuration can be modified with the exception of the Bit
Timing setting, as it does not join the bus activity. MCR[1] has to be cleared by writing a ‘0’ in
order to re-join the CAN bus. After this bit has been cleared, RCAN-ET waits until it detects 11
recessive bits, and then joins the CAN bus.
Note: After issuing a Halt request the CPU is not allowed to set TXPR or TXCR or clear MCR1
Note: Transition into or recovery from HALT mode, is only possible if the BCR1 and BCR0
Bit 2 : MCR2
0
1
until the transition to Halt mode is completed (notified by IRR0 and GSR4). After MCR1
is set this can be cleared only after entering Halt mode or through a reset operation (SW or
HW).
registers are configured to a proper Baud Rate.
Description
Transmission order determined by message identifier priority (Initial value)
Transmission order determined by mailbox number priority (Mailbox-15 →
Mailbox-1)
Section 19 Controller Area Network (RCAN-ET)
Rev. 1.00 Sep. 21, 2007 Page 741 of 1124
REJ09B0402-0100