r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 656

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 15 Synchronous Serial Communication Unit (SSU)
15.4.6
When bits CSS1 and CSS0 in SSCRH are set to B'10 and the SSUMS bit in SSCRL is cleared to
0, the SCS pin becomes an input pin (Hi-Z) before the serial transfer is started and after the serial
transfer is complete. Because of this, the SSU performs conflict error detection during these
periods. If a low level signal is input to the SCS pin during these periods, it is detected as a
conflict error. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0.
Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0
Rev. 1.00 Sep. 21, 2007 Page 630 of 1124
REJ09B0402-0100
Internally-clocked SCS
External input to SCS
Internal signal for
before resuming the transmission or reception.
SCS Pin Control and Conflict Error
transfer enable
SCS output
Figure 15.10 Conflict Error Detection Timing (Before Transfer)
MSS
CE
(Hi-Z)
detection period
Conflict error
Data written
to SSTDR
Worst time for
internal clocking of SCS