r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 177

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

(Example 1-5)
• Register specifications
(Example 1-6)
• Register specifications
<Channel B>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
Since instruction fetch is not a write cycle on channel A, a sequential condition does not
match. Therefore, no user break occurs.
BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BDRA = H'00000000,
BDMRA = H'00000000, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057,
BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000001, BETR = H'0005
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword
The number of execution-times break enable (5 times)
<Channel B>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword
On channel A, a user break occurs after the instruction of address H'00000500 is executed four
times and before the fifth time.
On channel B, a user break occurs before an instruction of address H'00001000 is executed.
BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BDRA = H'00000000,
BDMRA = H'00000000, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054,
BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address:
Data:
H'0003722E, Address mask: H'00000000
H'00000000, Data mask: H'00000000
H'00000500, Address mask: H'00000000
H'00000000, Data mask: H'00000000
H'00001000, Address mask: H'00000000
H'00000000, Data mask: H'00000000
H'00008404, Address mask: H'00000FFF
H'00000000, Data mask: H'00000000
Rev. 1.00 Sep. 21, 2007 Page 151 of 1124
Section 7 User Break Controller (UBC)
REJ09B0402-0100