r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 599

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Receiving Serial Data (Asynchronous Mode):
Figure 14.6 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCI for reception.
No
No
Read ORER, PER, and FER
Figure 14.6 Sample Flowchart for Receiving Serial Data (1)
Read RDRF flag in SCSSR
Clear RE bit in SCSCR to 0
PER, FER, or ORER = 1?
SCRDR, and clear RDRF
Read receive data in
flag in SCSSR to 0
All data received?
Start of reception
End of reception
flags in SCSSR
RDRF = 1?
No
Yes
Yes
Error handling
Yes
Section 14 Serial Communication Interface (SCI)
[1] Receive error handling and break
[2] SCI status check and receive data read:
[3] Serial reception continuation procedure:
detection:
PER, and FER flags in SCSSR to identify
the error. After performing the
appropriate error processing, ensure that
the ORER, PER, and FER flags are all
cleared to 0. Reception cannot be
resumed if any of these flags are set to 1.
In the case of a framing error, a break
can also be detected by reading the
value of the RXD pin.
then read the receive data in SCRDR
clear the RDRF flag to 0.
RDRF flag to 0 before the stop bit for the
current frame is received. The RDRF flag
is cleared automatically when the data
transfer controller (DTC) is activated to
read the SCRDR value, and this step is
not needed.
If a receive error occurs, read the ORER,
Read SCSSR and check that RDRF = 1,
To continue serial reception, clear the
Rev. 1.00 Sep. 21, 2007 Page 573 of 1124
REJ09B0402-0100