r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 261

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

9.5.8
Access to the on-chip FLASH for read is synchronized with Iφ clock and is executed in one clock
cycle. For details on programming and erasing, see section 22, Flash Memory.
Access to the on-chip RAM for read/write is synchronized with Iφ clock and is executed in one
clock cycle. For details, see section 23, RAM.
9.5.9
Table 9.9 shows the number of cycles required for access to the on-chip peripheral I/O registers by
the CPU.
Table 9.9
Notes: 1. When Iφ:Bφ = 8:1, n = 0 to 7
Synchronous logic and a layered bus structure have been adopted for this LSI. Data on each bus
are input and output in synchronization with rising edges of the corresponding clock signal. The L
bus, I bus, and peripheral bus are synchronized with the Iφ, Bφ, and Pφ clock, respectively. Figure
9.11 shows an example of the timing of write access to a register in 2Pφ cycle access with the
connected peripheral bus width of 16 bits when Iφ:Bφ:Pφ = 4:2:2. In access to the on-chip
peripheral I/O registers, the CPU requires three cycles of Iφ for preparation of data transfer to the I
bus after the data has been output to the L bus. After these three cycles, data can be transferred to
the I bus in synchronization with rising edges of Bφ. However, as there are two Iφ clock cycles in
Write
Read
2. The clock ratio of MIφ and MPφ does not affect the number of access cycles.
Access to On-Chip FLASH and On-Chip RAM by CPU
Access to On-Chip Peripheral I/O Registers by CPU
When Iφ:Bφ = 4:1, n = 0 to 3
When Bφ:Pφ = 4:1, m = 0 to 3
When Iφ:Bφ = 3:1, n = 0 to 2
When Bφ:Pφ = 3:1, m = 0 to 2
When Iφ:Bφ = 2:1, n = 0 to 1.
When Bφ:Pφ = 2:1, m = 0 to 1.
When Iφ:Bφ = 1:1, n = 0.
When Bφ:Pφ = 1:1, m = 0
n and m depend on the internal execution state.
Number of Cycles for Access to On-Chip Peripheral I/O Registers
Number of Access Cycles
(3 + n) × Iφ + (1 + m) × Bφ + 2 × Pφ
(3 + n) × Iφ + (1 + m) × Bφ + 2 × Pφ + 2 × Iφ
Rev. 1.00 Sep. 21, 2007 Page 235 of 1124
Section 9 Bus State Controller (BSC)
REJ09B0402-0100