r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 407

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r5f71374an80fpv

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r5f71374an80fpv
Description
32-bit Risc Microcomputer Superh?? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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11. Complementary PWM Mode 0% and 100% Duty Output
12. Toggle Output Synchronized with PWM Cycle
In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures
10.49 to 10.53 show output examples.
100% duty output is performed when the data register value is set to H'0000. The waveform in
this case has a positive phase with a 100% on-state. 0% duty output is performed when the
data register value is set to the same value as TGRA_3. The waveform in this case has a
positive phase with a 100% off-state.
On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-
off compare-match for the same phase occur simultaneously, both compare-matches are
ignored and the waveform does not change.
In complementary PWM mode, toggle output can be performed in synchronization with the
PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR).
An example of a toggle output waveform is shown in figure 10.54.
This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-
match between TCNT4 and H'0000.
The output pin for this toggle output is the TIOC3A pin. The initial output is 1.
Figure 10.54 Example of Toggle Output Waveform Synchronized with PWM Output
Toggle output
TIOC3A pin
TGRA_3
H'0000
TCNT_4
TCNT_3
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 1.00 Sep. 21, 2007 Page 381 of 1124
REJ09B0402-0100

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