r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 972

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 22 Flash Memory
(2) Interrupts during programming/erasing
Rev. 1.00 Sep. 21, 2007 Page 946 of 1124
REJ09B0402-0100
Though an interrupt processing can be executed at realtime during programming/erasing of the
downloaded on-chip program, the following limitations and notes are applied.
1. When flash memory is being programmed or erased, both the user MAT and user boot
2. Do not rewrite the program data specified by the FMPDR parameter. If new program data
3. Make sure the interrupt processing routine does not rewrite the contents of the flash-
4. At the beginning of the interrupt processing routine, save the CPU register contents. Before
5. When a transition is made to sleep mode or software standby mode in the interrupt
MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing
routine in on-chip RAM or external memory. Make sure the flash memory being
programmed or erased is not accessed by the interrupt processing routine. If flash memory
is read, the read values are not guaranteed. If the relevant bank in flash memory that is
being programmed or erased is accessed, the error protection state is entered, and
programming or erasing is aborted. If a bank other than the relevant bank is accessed, the
error protection state is not entered but the read values are not guaranteed.
is to provided by the interrupt processing, temporarily save the new program data in
another area. After confirming the completion of programming, save the new program data
in the area specified by FMPDR or change the setting in FMPDR to indicated the other
area in which the new program data was temporarily saved.
memory related registers or data in the downloaded on-chip program area. During the
interrupt processing, do not simultaneously perform RAM emulation, download of the on-
chip program by an SCO request, or programming/erasing.
returning from the interrupt processing, write the saved contents in the CPU registers again.
processing routine, the error protection state is entered and programming/erasing is
aborted.
If a transition is made to the reset state, the reset signal should only be released after
providing a reset input over a period longer than the normal 100 µs to reduce the damage to
flash memory.