r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 367

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r5f71374an80fpv

Manufacturer Part Number
r5f71374an80fpv
Description
32-bit Risc Microcomputer Superh?? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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10.4.4
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock upon overflow/underflow of
TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 10.44 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the
Table 10.44 Cascaded Combinations
For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional
input capture input pins can be specified by the input capture control register (TICCR). For input
capture in cascade connection, refer to section 10.7.22, Simultaneous Capture of TCNT_1 and
TCNT_2 in Cascade Connection.
Combination
Channels 1 and 2
Figure 10.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for
TGRC_0
TGRB_0
TGRA_0
TGRA_0
counters operates independently in phase counting mode.
H'0000
TIOCA
TCNT_0 value
Cascaded Operation
H'0200
H'0200
H'0200
Upper 16 Bits
TCNT_1
TGRC_0 to TGRA_0 Transfer Timing
H'0450
H'0450
Transfer
H'0450
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 1.00 Sep. 21, 2007 Page 341 of 1124
Lower 16 Bits
TCNT_2
H'0520
H'0520
REJ09B0402-0100
H'0520
Time

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