r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 678

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
16.3.4
ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and
acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits
received.
Rev. 1.00 Sep. 21, 2007 Page 652 of 1124
REJ09B0402-0100
Bit
7
6
5
I
2
Bit Name
TIE
TEIE
RIE
2
C Bus Interrupt Enable Register (ICIER)
C Bus Interface 2 (I
Initial value:
Initial
Value
0
0
0
R/W:
Bit:
2
C2)
R/W
TIE
7
0
R/W
R/W
R/W
R/W
TEIE
R/W
6
0
Description
Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1 or 0, this bit
enables or disables the transmit data empty interrupt
(IITXI).
0: Transmit data empty interrupt request (IITXI) is
1: Transmit data empty interrupt request (IITXI) is
Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt
(IITEI) at the rising of the ninth clock while the TDRE bit
in ICSR is 1. IITEI can be canceled by clearing the
TEND bit or the TEIE bit to 0.
0: Transmit end interrupt request (IITEI) is disabled.
1: Transmit end interrupt request (IITEI) is enabled.
Receive Interrupt Enable
This bit enables or disables the receive data full
interrupt request (IIRXI) and the overrun error interrupt
request (IIERI) in the clock synchronous format when
receive data is transferred from ICDRS to ICDRR and
the RDRF bit in ICSR is set to 1. IIRXI can be canceled
by clearing the RDRF or RIE bit to 0.
0: Receive data full interrupt request (IIRXI) are
1: Receive data full interrupt request (IIRXI) are
R/W
RIE
5
0
disabled.
enabled.
disabled.
enabled.
NAKIE
R/W
4
0
STIE
R/W
3
0
ACKE ACKBR ACKBT
R/W
2
0
R
1
0
R/W
0
0