r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 607

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Receiving Serial Data (Clock Synchronous Mode): Figure 14.12 shows a sample flowchart for
receiving serial data. Use the following procedure for serial data reception after enabling the SCIF
for reception.
When switching from asynchronous mode to clock synchronous mode, make sure that the ORER,
PER, and FER flags are all cleared to 0. If the FER or PER flag is set to 1, the RDRF flag will not
be set and data reception cannot be started.
No
No
Read receive data in SCRDR,
Figure 14.12 Sample Flowchart for Receiving Serial Data (1)
Read ORER flag in SCSSR
Clear RE bit in SCSCR to 0
Read RDRF flag in SCSSR
and clear RDRF flag
All data received?
Start of reception
End of reception
in SCSSR to 0
ORER = 1?
RDRF = 1?
No
Yes
Yes
Error handling
Yes
Section 14 Serial Communication Interface (SCI)
[1] Receive error handling:
[2] SCI status check and receive data read:
[3] Serial reception continuation procedure:
identify any error, perform the appropriate
error handling, then clear the ORER flag
to 0. Reception cannot be resumed while
the ORER flag is set to 1.
then read the receive data in SCRDR,
and clear the RDRF flag to 0. The
transition of the RDRF flag from 0 to 1
can also be identified by an RXI interrupt.
receive data register (SCRDR) and clear
the RDRF flag to 0 before the MSB (bit 7)
of the current frame is received. The
RDRF flag is cleared automatically when
the data transfer controller (DTC) is
activated by a receive-data-full interrupt
(RXI) request to read the SCRDR value,
and this step is not needed.
Read the ORER flag in SCSSR to
Read SCSSR and check that RDRF = 1,
To continue serial reception, read the
Rev. 1.00 Sep. 21, 2007 Page 581 of 1124
REJ09B0402-0100