r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 140

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 6 Interrupt Controller (INTC)
Rev. 1.00 Sep. 21, 2007 Page 114 of 1124
REJ09B0402-0100
Notes: I3 to I0 are interrupt mask bits in the status register (SR) of the CPU
Branch to exception
Save SR to stack
Save PC to stack
handling routine
Read exception
IRQOUT = high
execution state
IRQOUT = low
level to I3 to I0
Copy interrupt
1. IRQOUT is the same signal as the interrupt request signal to the CPU (see figure 6.1).
2. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when
3. The IRQOUT pin change timing depends on a frequency dividing ratio between the internal (I ) and bus (B )
vector table
User break?
Interrupt?
Program
level 14?
I3 to I0
Therefore, IRQOUT is output when the request priority level is higher than the level in bits I3–I0 of SR.
the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack).
However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted
and has output an interrupt request to the CPU, the IRQOUT pin holds low level.
clocks. This flowchart shows that the frequency dividing ratios of the internal (I ) and bus (B ) clocks are the same.
Yes
Yes
Yes
No
No
No
*
*
1
2
*
*
Figure 6.3 Interrupt Sequence Flowchart
3
3
NMI?
Yes
Yes
No
interrupt?
level 14?
Level 15
I3 to I0
No
Yes
Yes
No
interrupt?
level 13?
Level 14
I3 to I0
No
Yes
Yes
No
interrupt?
I3 to I0
level 0?
Level 1
No
Yes
No