r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 659

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

(2)
Figure 15.13 shows an example of transmission operation, and figure 15.14 shows a flowchart
example of data transmission. When transmitting data in clock synchronous communication mode,
the SSU operates as shown below.
In master mode, the SSU outputs a transfer clock and data. In slave mode, when a transfer clock is
input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock.
Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and
the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and
starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated.
When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to
SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been
transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time,
if the TEIE bit is set to 1, a TEI interrupt is generated.
While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit
is cleared to 0 before transmission.
User operation
LSI operation
Data Transmission
SSCK
TDRE
TEND
SSO
Data written
to SSTDR
TXI interrupt
generated
Figure 15.13 Example of Transmission Operation
(Clock Synchronous Communication Mode)
Bit 0
Data written
to SSTDR
Bit 1
1 frame
Section 15 Synchronous Serial Communication Unit (SSU)
Bit 7
TXI interrupt
generated
Rev. 1.00 Sep. 21, 2007 Page 633 of 1124
Bit 0
Bit 1
1 frame
REJ09B0402-0100
TEI interrupt
generated
Bit 7